| Author |
Lala, Parag K., 1948-
|
| Title |
An introduction to logic circuit testing / Parag K. Lala. |
| OCLC |
200808DCS017 |
| ISBN |
9781598293517 (electronic bk.) |
|
9781598293500 (pbk.) |
| ISBN/ISSN |
10.2200/S00149ED1V01Y200808DCS017 doi |
| Publisher |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, [2009] |
|
©2009 |
| Description |
1 electronic text (x, 99 pages : illustrations\.) : digital file. |
| LC Subject heading/s |
Logic circuits -- Testing.
|
|
Digital electronics -- Testing.
|
|
Integrated circuits -- Very large scale integration -- Testing.
|
| SUBJECT |
Digital circuits.
|
|
Logic circuit testing.
|
|
VLSI.
|
|
Fault detection.
|
|
Design-for-testability.
|
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Response evaluation techniques.
|
|
BIST.
|
|
D-Algorithm.
|
|
PODEM.
|
|
FAN.
|
|
LFSR.
|
| System details note |
Mode of access: World Wide Web. |
|
System requirements: Adobe Acrobat reader. |
| Bibliography |
Includes bibliographical references. |
| Contents |
Introduction -- Faults in logic circuits -- Stuck-at fault -- Bridging faults -- Delay fault -- Breaks and transistors stuck-open and stuck-on or stuck-open faults in CMOS -- Breaks -- Stuck-on and stuck-open faults -- Basic concepts of fault detection -- Controllability and observability -- Undetectable faults -- Equivalent faults -- Temporary faults -- References -- Fault detection in logic circuits -- Test generation for combinational logic circuits -- Truth table and fault matrix -- Path sensitization -- D-algorithm -- PODEM -- FAN -- Delay fault detection -- Testing of sequential circuits -- Designing checking experiments -- Test generation using the circuit structure and the state table -- References -- Design for testability -- Ad hoc techniques -- Scan-path technique for testable sequential circuit design -- Level-sensitive scan design -- Clocked hazard-free latches -- Double-latch and single-latch LSSD -- Random access scan technique -- Partial scan -- Testable sequential circuit design using nonscan techniques -- Crosscheck -- Boundary scan -- References -- Built-in self-test -- Test pattern generation for BIST -- Exhaustive testing -- Pseudoexhaustive pattern generation -- Pseudorandom pattern generator -- Deterministic testing -- Output response analysis -- Transition count -- Syndrome checking -- Signature analysis -- BIST architectures -- Built-in logic block observer -- Self-testing using an MISR and parallel shift register sequence generator -- LSSD on-chip self-test. |
| Restrictions |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
|
Access may be restricted to authorized users only. |
|
Unlimited user license access |
| NOTE |
Compendex. |
|
Google scholar. |
|
Google book search. |
| Summary |
An Introduction to Logic Circuit Testing provides a detailed coverage of techniques for test generation and testable design of digital electronic circuits/systems. The material covered in the book should be sufficient for a course, or part of a course, in digital circuit testing for senior-level undergraduate and first-year graduate students in Electrical Engineering and Computer Science. The book will also be a valuable resource for engineers working in the industry. This book has four chapters. Chapter 1 deals with various types of faults that may occur in very large scale integration (VLSI)-based digital circuits. Chapter 2 introduces the major concepts of all test generation techniques such as redundancy, fault coverage, sensitization, and backtracking. Chapter 3 introduces the key concepts of testability, followed by some ad hoc design-for-testability rules that can be used to enhance testability of combinational circuits. Chapter 4 deals with test generation and response evaluation techniques used in BIST (built-in self-test) schemes for VLSI chips. |
| NOTE |
INSPEC. |
| Additional physical form available note |
Also available in print. |
| General note |
Part of: Synthesis digital library of engineering and computer science. |
|
Title from PDF t.p. (viewed on December 3, 2008). |
|
Series from website. |
|
