| Author |
Davis, Justin S., 1975-
|
| Title |
Finite state machine datapath design, optimization, and implementation / Justin Davis, Robert Reese. |
| OCLC |
200702DCS014 |
| ISBN |
1598295306 (electronic bk.) |
|
9781598295306 (electronic bk.) |
|
1598295292 (pbk.) |
|
9781598295290 (pbk.) |
| ISBN/ISSN |
10.2200/S00087ED1V01Y200702DCS014 doi |
| Publisher |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, [2008] |
|
©2008 |
| Description |
1 electronic text (ix, 113 pages : illustrations\.) : digital file. |
| LC Subject heading/s |
Electronic digital computers -- Design and construction.
|
| SUBJECT |
Verilog.
|
|
Datapath.
|
|
Scheduling.
|
|
Latency.
|
|
Throughput.
|
|
Timing.
|
|
Pipelining.
|
|
Memories.
|
|
FPGA.
|
|
Flowgraph.
|
| System details note |
Mode of access: World Wide Web. |
|
System requirements: Adobe Acrobat Reader. |
| Bibliography |
Includes bibliographical references. |
| Contents |
Chapter 1. Calculating maximum clock frequency -- Chapter 2. Improving design performance -- Chapter 3. Finite state machine with datapath (FSMD) design -- Chapter 4. Embedded memory usage in finite state machine with datapath (FSMD) designs. |
| Restrictions |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
|
Access may be restricted to authorized users only. |
|
Unlimited user license access |
| NOTE |
Compendex. |
|
Google scholar. |
|
Google book search. |
| Summary |
Finite State Machine Datapath Design, Optimization, and Implementation explores the design space of combined FSM/Datapath implementations. The lecture starts by examining performance issues in digital systems such as clock skew and its effect on setup and hold time constraints, and the use of pipelining for increasing system clock frequency. This is followed by definitions for latency and throughput, with associated resource tradeoffs explored in detail through the use of dataflow graphs and scheduling tables applied to examples taken from digital signal processing applications. Also, design issues relating to functionality, interfacing, and performance for different types of memories commonly found in ASICs and FPGAs such as FIFOs, single-ports, and dual-ports are examined. Selected design examples are presented in implementation-neutral Verilog code and block diagrams, with associated design files available as downloads for both Altera Quartus and Xilinx Virtex FPGA platforms. A working knowledge of Verilog, logic synthesis, and basic digital design techniques is required. This lecture is suitable as a companion to the synthesis lecture titled Introduction to Logic Synthesis using Verilog HDL. |
| NOTE |
INSPEC. |
| Additional physical form available note |
Also available in print. |
| General note |
Part of: Synthesis digital library of engineering and computer science. |
|
Title from PDF t.p. (viewed on October 11, 2008). |
|
Series from website. |
|
