| Author |
Jacob, Bruce L.
|
| Title |
The memory system : you can't avoid it, you can't ignore it, you can't fake it / Bruce Jacob ; with contributions by Sadagopan Srinivasan, David T.Wang. |
| OCLC |
200907CAC007 |
| ISBN |
9781598295887 (electronic bk.) |
|
9781598295870 (pbk.) |
| ISBN/ISSN |
10.2200/S00201ED1V01Y200907CAC007 doi |
| Publisher |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, [2009] |
|
©2009 |
| Description |
1 electronic text (viii, 69 pages : illustrations\.) : digital file. |
| LC Subject heading/s |
Computer storage devices.
|
|
Memory management (Computer science)
|
| SUBJECT |
Memory systems.
|
|
Storage systems.
|
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Memory scheduling.
|
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System simulation.
|
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Memory system design.
|
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Prefetching.
|
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Hash-associative cache.
|
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Virtual memory.
|
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Superpages.
|
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Memory power.
|
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Storage power.
|
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Translation lookaside buffers.
|
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Cache design.
|
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DRAM systems.
|
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Memory bandwidth.
|
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Memory latency.
|
|
Memory trends.
|
| System details note |
Mode of access: World Wide Web. |
|
System requirements: Adobe Acrobat reader. |
| Bibliography |
Includes bibliographical references (pages 65-68). |
| Contents |
Prelude: Why should I care about the memory system -- Primers -- Your code does not run in a vacuum -- Data and its representation -- Variables and stack allocation -- Random access is anything but -- Performance perspective -- Memory-system organization and operation -- State of the (DRAM) union -- It must be modeled accurately -- Some context -- Modeling the memory system -- Comparing the models -- Let's add prefetching to the mix -- Summary -- And it will change soon -- Problems and trends -- The use of multiple cores increases working-set demands -- Multicore bandwidth requirement is roughly 1GB/s per core -- TLB reach does not scale well (... or at all, really) -- You cannot physically connect to all the DRAM you can afford to purchase -- DRAM refresh is becoming expensive in both power and time -- Flash is eating disk's lunch -- For large systems, power dissipation of DRAM exceeds that of CPUs -- On-chip cache hierarchies are complex -- Disk access is still slow -- There are too many wires on a typical motherboard as it is -- Numerous new technologies are in development -- Some obvious conclusions -- A new DRAM-system organization is needed -- Flash needs to be integrated -- Possibly revisit superpages -- Some suggestions -- Fully buffered DIMM, take 2 (aka "BOMB") -- Some uses for flash -- Superpages (take 2) and SuperTLBs -- The hash-associative cache -- Virtual memory in the age of cheap memory -- Postlude: you can't fake it -- Bibliography -- Biography. |
| Restrictions |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
|
Access may be restricted to authorized users only. |
|
Unlimited user license access |
| NOTE |
Compendex. |
|
INSPEC. |
|
Google book search. |
| Abstract |
Today, computer-system optimization, at both the hardware and software levels, must consider the details of the memory system in its analysis; failing to do so yields systems that are increasingly inefficient as those systems become more complex. This lecture seeks to introduce the reader to the most important details of the memory system; it targets both computer scientists and computer engineers in industry and in academia. Roughly speaking, computer scientists are the users of the memory system, and computer engineers are the designers of the memory system. Both can benefit tremendously from a basic understanding of how the memory system really works: the computer scientist will be better equipped to create algorithms that perform well, and the computer engineer will be better equipped to design systems that approach the optimal, given the resource limitations. Currently, there is consensus among architecture researchers that the memory system is "the bottleneck," and this consensus has held for over a decade. Somewhat inexplicably, most of the research in the field is still directed toward improving the CPU to better tolerate a slow memory system, as opposed to addressing the weaknesses of the memory system directly. This lecture should get the bulk of the computer science and computer engineering population up the steep part of the learning curve. Not every CS/CE researcher/developer needs to do work in the memory system, but, just as a carpenter can do his job more efficiently if he knows a little of architecture, and an architect can do his job more efficiently if he knows a little of carpentry, giving the CS/CE worlds better intuition about the memory system should help them build better systems, both software and hardware. |
| NOTE |
Google scholar. |
| Additional physical form available note |
Also available in print. |
| General note |
Part of: Synthesis digital library of engineering and computer science. |
|
Title from PDF t.p. (viewed on July 8, 2009). |
|
Series from website. |
|
