| Author |
Smith, Scott C.
|
| Title |
Designing asynchronous circuits using NULL convention logic (NCL) / Scott C. Smith and Jia Di. |
| OCLC |
200907DCS023 |
| ISBN |
9781598299823 (electronic bk.) |
|
9781598299816 (pbk.) |
| ISBN/ISSN |
10.2200/S00202ED1V01Y200907DCS023 doi |
| Publisher |
San Rafael, Calif. (1537 Fourth Street, San Rafael, CA 94901 USA) : Morgan & Claypool Publishers, [2009] |
|
©2009 |
| Description |
1 electronic text (x, 86 pages : illustrations\.) : digital file. |
| LC Subject heading/s |
Asynchronous circuits -- Design and construction.
|
|
Combinational circuits.
|
|
Sequential circuits.
|
|
Logic, Symbolic and mathematical.
|
|
Logic design.
|
| SUBJECT |
Computer engineering.
|
|
Digital design.
|
|
Asynchronous logic.
|
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Delay-insensitive logic.
|
|
Combinational logic.
|
|
Sequential logic.
|
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NULL Convention Logic.
|
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NCL.
|
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Input-completeness.
|
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Observability.
|
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Dual-rail.
|
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Quad-rail.
|
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Pipelining.
|
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Embedded registration.
|
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Early completion.
|
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NULL cycle reduction.
|
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Wavefront steering.
|
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MTCMOS.
|
| System details note |
Mode of access: World Wide Web. |
|
System requirements: Adobe Acrobat reader. |
| Bibliography |
Includes bibliographical references. |
| Contents |
Introduction to asynchronous logic -- Overview of NULL convention logic (NCL) -- NCL system framework and fundamental components -- Transistor-level NCL gate design -- Combinational NCL circuit design -- Input-completeness and observability -- Dual-rail NCL design -- Quad-rail NCL design -- Sequential NCL circuit design -- NCL implementation of Mealy and Moore machines -- NCL implementation of algorithmic state machines -- NCL throughput optimization -- Pipelining -- Embedded registration -- Early completion -- NULL cycle reduction -- Low-power NCL design -- Wavefront steering -- Multi-threshold CMOS (MTCMOS) for NCL (MTNCL) -- MTCMOS for synchronous circuits -- Implementing MTCMOS in NCL circuits -- Comprehensive NCL design example. |
| Restrictions |
Abstract freely available; full-text restricted to subscribers or individual document purchasers. |
|
Access may be restricted to authorized users only. |
|
Unlimited user license access |
| NOTE |
Compendex. |
|
Google scholar. |
|
Google book search. |
| Abstract |
Designing Asynchronous Circuits using NULL Convention Logic (NCL) begins with an introduction to asynchronous (clockless) logic in general, and then focuses on delay-insensitive asynchronous logic design using the NCL paradigm. The book details design of input-complete and observable dual-rail and quad-rail combinational circuits, and then discusses implementation of sequential circuits, which require datapath feedback. Next, throughput optimization techniques are presented, including pipelining, embedding registration, early completion, and NULL cycle reduction. Subsequently, low-power design techniques, such as wavefront steering and Multi-Threshold CMOS (MTCMOS) for NCL, are discussed. The book culminates with a comprehensive design example of an optimized Greatest Common Divisor circuit. Readers should have prior knowledge of basic logic design concepts, such as Boolean algebra and Karnaugh maps. After studying this book, readers should have a good understanding of the differences between asynchronous and synchronous circuits, and should be able to design arbitrary NCL circuits, optimized for area, throughput, and power. |
| NOTE |
INSPEC. |
| Additional physical form available note |
Also available in print. |
| General note |
Part of: Synthesis digital library of engineering and computer science. |
|
Title from PDF t.p. (viewed on August 9, 2009). |
|
Series from website. |
|
